A level shifter alters the magnitude of a signal. They are often utilized to convert digital signals operating in one domain to signals in a different domain. For example, a level shifter might take in an analog signal from a circuit operating with a supply voltage of 1 volt, and transfer the signal into a circuit operating with a supply voltage of 2 volts. In this example, each value of the signal in the 1 volt domain would be represented by a factor of two larger value of the signal in the 2 volt domain. As another example, a level shifter might take in a digital signal operating with a transistor-transistor logic level and convert the signal to different domain. Since digital signals are either logic high or logic low values, the transistor-transistor logic level digital signal would be level shifted to a create a new version of the signal with logic high and logic low values equivalent to the logic high and logic low values of the new domain.
A level shifter architecture can be described with reference to the block diagram in FIG. 1 in which circuit 100 is a level shifter. Level shifter 100 shifts a signal Din that varies between a supply voltage 101 and ground 102 to a signal Dout that varies between a high supply voltage 103 and a low supply voltage 104. The magnitude of the difference between the supply voltage and ground is less than the magnitude of the difference between the high and low supply voltages. For example, the supply voltage could be 1.8 volts, ground could be 0 volts, the high supply voltage could be 3.5 volts, and the low supply voltage could be −3.5 volts. Level shifter 100 is double sided because it shifts both the upper and lower bounds of the input signal Din. To do this, it utilizes two different single sided level shifters: positive level shifter 105 and negative level shifter 106. Each of these single sided level shifters has an output connected to the gate of an output buffer device. Positive level shifter 105 is connected to the gate of p-type field effect transistor (p-FET) 107 and negative level shifter 106 is connected to the gate of n-type field effect transistor (n-FET) 108.
A circuit powered by high supply voltage 103 and low supply voltage 104 has the potential to consume more power than a circuit that is powered by supply 101 and ground 102. Furthermore, the high and low supply voltages 103 and 104 are, in the context of an integrated circuit, usually generated on chip using a pump circuit so that the amount of power available at those voltages levels is somewhat limited. Therefore, it is important to assure that p-FET 107 and n-FET 108 are never placed in a conductive state at the same time. If this were so, a short circuit path would exist between high supply voltage 103 and low supply voltage 104 which would burn up a significant amount of power. The short circuit condition described is prevented through the use of phase logic 109. This phase logic controls the times in which a signal is provided to positive level shifter 105 and negative level shifter 106 to assure that their associated output buffer devices (i.e., p-FET 107 and n-FET 108) are never in a conductive state at the same time. Phase logic 109 serves to assure that, during transitions in Din, the output buffer device that is transitioning to a nonconductive state does so before the other output buffer device transitions to a conductive state.
If an inverted version of Dout is desired, additional circuitry is required. An inverted version of Dout can be referred to as Doutn. Placing an inverter at node Dout to generate Doutn is not sufficient for most applications because it is desirable to have a phased matched version of Dout and Doutn available. If a simple inverter was utilized to generate Doutn from Dout, the inverter would introduce a phase difference between the two signals equal to the delay of that inverter. Therefore, a phased matched inverted version must be generated separately and concurrently with the generation of the original non-inverted signal. This is accomplished through the use of two additional output buffer devices: p-FET 110 and n-FET 111; and positive and negative level shifters similar to those used to generate the original signal: positive level shifter 112 and negative level shifter 113.
Common circuits that can be used in place of level shifter 105 and negative level shifter 106 naturally produce complementary output signals. The complementary output signals from these common circuits could have been used to generate the inverted version of the output signal. However, because phase delay was purposefully introduced to the system at an earlier point, these complementary signals will not have the proper phasing for controlling the additional set of output buffer devices such as p-FET 110 and n-FET 111. In other words, while the outputs of level shifter 105 and 106 are appropriately shifted so that output buffer devices 107 and 108 are never on at the same time and power is conserved, if the complementary signals of level shifters 105 and 106 were applied to output buffer devices 110 and 111 they would instead assure that the output buffer devices were on at the same time and that power is wasted.